1. Field of the Invention
The present invention relates to a multilayer capacitor, and more specifically, to a multilayer capacitor including a ceramic layer and at least a pair of internal electrodes opposed to each other with the ceramic layer provided therebetween, a circuit board, a circuit module, and a method for manufacturing a multilayer capacitor.
2. Description of the Related Art
In a power supply circuit, when variations in voltage of a power supply line is increased, the impedance in the power supply line and ground causes an unstable operation of a circuit to be driven, interference between circuits through the power supply circuit, or oscillation. Therefore, a decoupling capacitor is typically connected between a power supply line and ground. The decoupling capacitor functions to decrease an alternating current impedance between the power supply line and the ground, thereby suppressing variation in power supply voltage and interference between circuits.
In communication apparatuses such as cellular phones and information processing apparatuses such as personal computers, the signal speed has been increasing for processing a large amount of information in recent years. Accordingly, the clock frequencies of the semiconductor integrated circuits (referred to as “IC” hereinafter) have been increasing. As a result, noise including many harmonic components often occurs, and thus, stronger decoupling is required for IC power supply circuits.
In order to enhance a decoupling effect, it is effective to use a decoupling capacitor having excellent impedance frequency characteristics. As such a decoupling capacitor, a multilayer ceramic capacitor may be used. A multilayer ceramic capacitor has low ESL (Equivalent Series Inductance) and thus, exhibits a high noise absorbing effect over a wide frequency band as compared to an electrolytic capacitor.
A known multilayer capacitor capable of decreasing ESL is shown in FIG. 12. Specifically, as shown in FIG. 12, a known multilayer capacitor 201 includes a laminate 202 in which a plurality of ceramic layers is laminated, at least a pair of a first internal electrode 203 and a second internal electrode 204 which are opposed to each other through the ceramic layer, first and second external electrodes 205 and 206 which are provided on the upper surface, third and fourth external electrodes 207 and 208 which are provided on the lower surface, first via conductors 209 for electrically connecting the first external electrodes 205, the first internal electrode 203, and the third external electrodes 207, and second via conductors 210 for electrically connecting the second external electrodes 206, the second internal electrode 204, and the fourth external electrodes 208.
In the multilayer capacitor 201, the first and second via conductors 209 and 210 having different polarities are alternately disposed, and thus, the magnetic fields produced around the first via conductors 209 and the magnetic fields produced around the second via conductors 210 are canceled by each other, thereby decreasing ESL. Further, the first and second external electrodes 205 and 206 and the third and fourth external electrodes 207 and 208 are provided on the upper and lower surfaces, respectively, of the laminate 202. Therefore, the multilayer capacitor 201 can be easily mounted between an IC and amounting substrate, and the distance between the multilayer capacitor 201 and IC can be decreased. As a result, in the multilayer capacitor 201, a higher decoupling effect is obtained.
In recent years, electronic components have been increasingly miniaturized. Therefore, the multilayer capacitor 201 shown in FIG. 12 must be decreased in thickness. As described above, this is because it is necessary to mount the multilayer capacitor 201 in the space between the IC and the mounting substrate or in the mounting substrate.
Further, the multilayer capacitor 201 is connected to the IC through a pin. Therefore, it is necessary that the first and second external electrodes 205 and 206 of the multilayer capacitor 201 have a connectable positional relationship to the pin of the IC. Thus, the dimensions of a main surface of the multilayer capacitor 201 depend on the dimensions of a main surface of the IC. For these reasons, the multilayer capacitor 201 has a thin plate shape.
However, the thin plate-shaped multilayer capacitor 201 has a problem in that it is easily curved during firing. When the multilayer capacitor 201 is curved during firing, the first and second external electrodes 205 and 206 and the third and fourth external electrodes 207 and 208 are not arranged in the same planes, thereby causing large variations in the distances between the multilayer capacitor 201 and the IC and between the multilayer capacitor 201 and the mounting substrate. As a result, the problem of causing incomplete electrical connections between the multilayer capacitor 201 and IC and between the multilayer capacitor 201 and the mounting substrate occurs.
With respect to this problem, Japanese Unexamined Patent Application Publication No. 2006-032747 discloses a multilayer electronic component in which the height of an external electrode is greater than an amount of curvature of a ceramic laminate. Specifically, conductive paste for external electrodes is applied twice, and the printing area in the upper stage is decreased so as to increase the height of external electrodes.
However, two conductive paste coating steps are undesirable because the number of steps is increased. In addition, when the printing areas in the upper and lower stages of external electrodes are different, it is necessary to prepare two types of printing plates for screen printing. Furthermore, even when the height of external electrodes is increased as in the multilayer electronic component described in Japanese Unexamined Patent Application Publication No. 2006-032747, the occurrence of curvatures causes variations in height of the external electrodes.
Relevant patent documents other than Japanese Unexamined Patent Application Publication No. 2006-032747 include Japanese Unexamined Patent Application Publication Nos. 11-111766, 2003-318064, 2003-318065, and 2004-153040. Japanese Unexamined Patent Application Publication No. 11-111766 discloses a wiring board in which a plating metal layer is deposited on at least the end of a projecting portion of a via conductor, and the height of the surface of the plating metal layer from the upper surface of an insulating substrate is about 10 μm to about 50 μm. Japanese Unexamined Patent Application Publication No. 2003-318064 discloses a multilayer capacitor in which the ends of first and second via hole conductors exposed in the two main surfaces of a laminate project from the main surfaces of the laminate, and one of the ends of each of the first and second via hole conductors projecting from the main surfaces of the laminate is coated with an oxide film. Japanese Unexamined Patent Application Publication No. 2003-318065 discloses a multilayer electronic component in which a via conductor passing through at least one of an uppermost insulating layer and a lowermost insulating layer of a laminate has a projecting portion integrally provided therein and projecting from the surface of the insulating layer. Japanese Unexamined Patent Application Publication No. 2004-153040 discloses a multilayer capacitor including a first terminal electrode formed by projecting a portion of a first via conductor, which is electrically connected to a first internal electrode layer and provided along the lamination direction of dielectric layers, from at least one of the two outermost surfaces substantially perpendicular to the lamination direction so as to have substantially the same outer diameter as that of the first via conductor, a first mounting terminal which has a first conductor pad electrically connected to the first terminal electrode and which is configured to have an outer diameter greater than that of the first terminal electrode and cover the first terminal electrode, a second terminal electrode formed by projecting a portion of a second via conductor, which is electrically connected to a second internal electrode layer and provided along the lamination direction, from at least one of the two outermost surfaces substantially perpendicular to the lamination direction so as to have substantially the same outer diameter as that of the second via conductor, and a second mounting terminal which has a second conductor pad electrically connected to the second terminal electrode and which is configured to have an outer diameter larger than that of the second terminal electrode and cover the second terminal electrode.